1. Technical field of the Invention
The present invention relates to a semiconductor device, particularly an inexpensive, small-sized and high-output semiconductor device, and a process for manufacturing the same.
2. Description of Related Arts
Field-effect transistors (FET) using compound semiconductors such as gallium arsenide (GaAs) and the like have been conventionally used as the main devices of equipment for use in satellite and mobile communications because of their high frequency and high output characteristics. With the recent drastic advance in information technology, further improvement in performance, cost and size are demanded for FETs.
FIGS. 17 and 18 show a conventional discrete type high-output multi-finger FET chip (200) for use in a transmission amplifier for mobile communication. The FET chip (200) has a rectangular substrate (202) formed of semi-insulating gallium arsenide. An insulating region (204) and an active region (206), not overlapped on each other, are formed on one surface of the substrate (202) (the upper side in FIG. 18). A number of FET elements (hereinafter referred to as xe2x80x9cFET unitsxe2x80x9d) are formed on the active region (206). The FET unit includes a narrow gate a electrode (208) which extends parallel to the direction of the shorter edge of the FET chip (200) (in the Y-axial direction in FIG. 17), a source wire (210) and a drain wire (212). The gate electrode (208) is directly formed at a regular interval on the substrate (202). On the other hand, the source wire (210) and the drain wire (212) are arranged on the substrate (202) through a source electrode (226) and a drain electrode (228), respectively, and the source wire (210) and the drain wire (212) are opposed to each other through the gate electrode (208).
The gate electrode (208) is electrically connected to a gate feeder (222) which is arranged along the longer edge of the substrate (202). The gate feeder (222) is electrically connected to a gate pad (214) which is arranged on a portion of the insulating region adjacent to one of the longer edges of the substrate (202). A source pad (216) is arranged between each of adjacent gate pads (214). The source pad (216) and the source wire (210) are electrically connected to each other through an air bridge (210f) which is located therebetween above the gate feeder (222). On the other hand, the drain wire (212) is electrically connected to a drain pad (218) which is arranged on a portion of the insulating region adjacent to another longer edge of the substrate (202).
A via-hole (220) penetrating the substrate (202) is formed in each of the source pads (216), and through this via-hole (220), each of the source pads (216) is electrically connected to a gold plated layer (232) on the other side of the substrate (202).
In the FET chip (200) thus constructed, a current supplied to the source pad (216) passes through the source wire (210), the source electrode (226), a portion of the active layer adjacent to the gate electrode (208), namely a channel (230), the next drain electrode (228), and further the drain pad (218) through the drain wire (212). At this stage, by increasing or decreasing the voltage applied to the gate electrode (208), the current flowing from the source pad (216) to the drain pad (218) can be varied.
The FET chip (200) also has a plurality of gate electrodes (208) which are arranged in parallel. The total width of the plurality of gate electrodes (208) is very wide, so that the FET chip (200) can generate high output when a great amount of current is allowed to pass therethrough.
Specifically, the FET chip (200) shown in FIG. 17 is used an amplifier of a frequency of 1 to 2 GHz and an output power of 100 watts. In this case, each of the gate electrodes (208) is about 900 xcexcm in width. There are arranged one hundred gate electrodes (208), and thus, the total width of the gate electrodes (the length of the gate layer) is about 100 mm.
FIGS. 19 and 20 show a high output FET chip (250) having a source island via-hole (SIV) structure provided with a heat sink. In this FET chip (250), two source electrodes (226) are arranged in parallel between each of adjacent gate electrodes (208). A slot-like via-hole (220) is formed between two source electrodes (226) A parallel thereto, and through this via-hole (220), the two source electrodes (226) are electrically connected to a gold plated layer (232) which is provided on the reverse surface of the substrate (202) as a heat sink for releasing heat.
The gold plating layer (232) can be used as an earth electrode. In this case, the distance between the source electrode (226) and the earth becomes shorter, so that the parasitic inductance is decreased. Therefore, the FET chip (250) is particularly suited for use in a high frequency range.
It is needed to increase the drain current and/or to improve the withstand voltage of the FET chip (200) between the gate and the drain in order to enhance the output features of the foregoing FET chip (200). The withstanding voltage between the gate and the drain varies depending upon the withstanding voltage of each of the FET units. On the other hand, in order to increase the drain current, it is necessary to increase the total width of the gate electrodes. Then, in order to increase the total width of the gate electrodes, it is necessary to increase the number of FET units and the width of the gate electrode of the FET units. In this case, there arises a new problem in that the size of the FET chip becomes larger.
There are several restrictions in decreasing the size of the FET chip. This will be described in detail hereinafter. A large current flows between the source and the drain. For example, during an operation, alternating current flows between the source and the drain, and an average current per unit width of the gate is about 200 mA/mm, and the maximal current is larger than the average current. To allow the maximal current to flow, certain widths are needed between the source electrode (226) and the drain electrode (228), and between the source wire (210) and the drain wire (212).
However, the FET chip (200) shown in FIGS. 17 and 18 has a problem in that, while it is possible to allow a comparatively large current to flow to the source wire (210) in contact with the source electrode (226) and to the drain wire (212) in contact with the drain electrode (228), there is a limit, to the current which flows to the air bridge (210f) because the section of the air bridge (210f) for connecting the source wire (212) to the source pad (216) is small. Therefore, the allowable current of the FET chip (200) is determined depending on the allowable current of the air bridge (210f).
In addition, the thickness of the air bridge (210f) is as comparatively high as several micrometers. Therefore, it is difficult to narrow the interval between each of adjacent air bridges (210f) (in other words, to increase the width of the air bridge (210f)) when the thickness of a photoresist layer for forming the air bridge (210f) is increased. For this reason, it is not easy to narrow the width of the FET chip (200) in the X-axis direction in FIG. 17.
Also, the FET chip (250) shown in FIGS. 19 and 20 has the following problem. As mentioned above, a via-hole (210) is located between a pair of source electrodes (226). In order to form such a via-hole (210), it is necessary for the FET chip (250) to have a certain length in the X-axis direction in FIG. 20. Therefore, to achieve high output from the FET chip (250), the FET chip (250) must have a at certain length in the X-axis direction. Thus, there is a limit to decreasing the length of the FET chip in the X-axis direction.
In this regard, the high output FETs having heat sink structures are already described in Japanese Kokoku Patent Publication Nos. 7-77265 and 8-21598. However, these semiconductor devices are not intended to have smaller dimensions by an optimized arrangement of semiconductor elements which compose the semiconductor devices.
The present invention is addressed to those aforementioned problem, the object of the present invention is to provide a high output semiconductor device in which the area of the chip is diminished any change in the conventional design rules. The second object of the present invention is to provide a process for constructing a small-sized and high output semiconductor device using simple steps.
In order to achieve the foregoing subject matters, the present invention provides a semiconductor device which comprises:
(a) a semiconductor substrate having a first surface and a second side;
(b) an active region formed on the first surface of the substrate;
(c) a first semiconductor element formed on the active region, including
first and second channel region formed so that the width directions of the channels are substantially perpendicular to each other,
a first source electrode and a first drain electrode, which are formed adjacent to the first and second channel regions and opposing to each other with the first and second channel regions therebetween, and which are in ohmic contact with the active region, and
a first gate electrode which is formed on the first and second channel regions and along the first source electrode and the first drain electrode, and which is bent at least one bending position; and
(d) a second semiconductor element formed on the active region so as to be adjacent to the first semiconductor element, including
third and fourth channel regions which are formed adjacent to the first and second channel regions, respectively, with the first source electrode or the first drain electrode therebetween,
a second source electrode or a second drain electrode which is formed opposing the first drain electrode or the first source electrode through the third and fourth channel regions, and which is in ohmic contact with the surface of the active region, and
a second gate electrode which is formed on the third and fourth channel regions and along the second source electrode or the second drain electrode, and which is bent at least one bending position.
It becomes possible to increase the width of the gate without increasing the length of the shorter side of the active region, by employing the above structure.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the source electrode and the drain electrode are composed of band electrodes, and that the bending position of the first gate electrode and the bending position of the second gate electrode are arranged on a straight line substantially in parallel with the longer side of the active region.
It becomes possible to increase the width of the gate without increasing the length of the shorter side of the active region, by employing the above structure.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the following are further comprised of:
a source-drawing wire which is formed on the source electrode and along the source electrode;
a source common wire connected to the source-drawing wire;
a drain-drawing wire which is formed on the drain electrode and along the drain electrode;
a drain common wire connected to the drain-drawing wire; and
a gate common wire connected to the gate electrode, wherein the drain common wire is formed opposing the source common wire and the gate common wire through the active region, and wherein the source-drawing wire is connected to the source common wire through an air bridge across the gate common wire.
It becomes possible to lessen uniformity in electric operation by employing the above structure. Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that insulating regions are formed on the semiconductor substrate and under the bending position of the first gate electrode and the bending position of the second gate electrode.
It becomes possible to reduce the concentration of electric field around the bending position of the gate electrode, by employing the above structure.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the first source electrode is formed in the rectangular shape, two sides of which are adjacent to the first and second channel regions, respectively, and that the source electrode is connected to a conductive film formed on the second surface of the semiconductor substrate, through a via-hole formed in the source electrode.
It becomes possible to increase the width of the gate without increasing the shorter side of the active region also in a FET having SIV structure, by employing the above structure. In addition, the area of the source electrode can be reduced, so that the semiconductor device can be constructed at high density.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that insulating regions are formed on the semiconductor substrate and under the bending position of the first gate electrode and the bending position of the second gate electrode.
It becomes possible to reduce the concentration of electric field around the bending position of the gate electrode, by employing the above structure.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the insulating region is formed so that the width of the first second channel region is narrower than the width of the source electrode adjacent to the channel region.
It becomes possible to electrically neutralize the corner of the source electrode by employing the above structure, so that the concentration of electric field on the corner of the source electrode can be prevented.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the first gate electrode has two bending positions at which the bending directions of the first gate electrode are reversed to each other, and that the second gate electrode has such two bending positions that allow the second gate electrode to extend substantially in parallel with the first gate electrode.
The gate pad and the drain pad can be formed on the same surface of the semiconductor substrate, and thus, the construction of the semiconductor device becomes easy.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the first gate electrode and the second gate electrode are arranged in parallel with each other and are connected to a common pad electrode which is formed on the bending position of the first gate electrode and the bending position of the second gate electrode.
It becomes possible to prevent a decrease in the high frequency features which occurs when the gate width is increased, by employing the above structure.
It is preferable that the semiconductor substrate is made of electrically isotropic compound.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the first gate electrode and the second gate electrode share the first source electrode or the first drain electrode.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the first gate electrode is bent in a vertical direction at the bending position.
Also, the present invention provides a semiconductor device according to the foregoing semiconductor device and characterized in that the angle formed by the width direction of the first gate electrode and the longer side direction of the active region is substantially 45xc2x0.
In another aspect, the present invention provides a process for manufacturing a semiconductor device, which comprises the steps of:
setting a semiconductor substrate having a first surface and a second surface,
forming an active region on the first surface of the substrate,
forming a first channel region and a second channel region on the active region so that the width directions of both channels are substantially perpendicular to each other,
forming a gate electrode on the first and second channel regions so that the gate electrode bends at a bending position and extends along the first and second channel regions, and
forming a source electrode and a drain electrode substantially in parallel with the gate electrode so that the source electrode and the drain electrode oppose to each other through the first and second channel regions.
By employing the above process, a small-sized semiconductor device can be manufactured by simple steps.
Also, the present invention provides a process according to the foregoing process and characterized by further comprising the step of forming an insulating region on the semiconductor substrate and under the bending position of the gate electrode.
Also, the present invention provides a process according to the foregoing process and characterized by further comprising the steps of forming a conductive film on the second side of the semiconductor substrate, and electrically connecting the source electrode to the conductive film through the via-hole penetrating the semiconductor substrate.
It is preferable that the source electrode is formed in the rectangular shape.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the sprit and scope of the invention will become apparent to those skilled in the art from this detailed description.